Files
Akhil Velagapudi 8e9c355a3f Disallow dots in names (#150)
* Disallow dots in names

Signed-off-by: akhilles <akhilvelagapudi@gmail.com>

* Bump stdlib

Signed-off-by: akhilles <akhilvelagapudi@gmail.com>

* Simplify is_instance_position

Signed-off-by: akhilles <akhilvelagapudi@gmail.com>

* Update snapshot

Signed-off-by: akhilles <akhilvelagapudi@gmail.com>

---------

Signed-off-by: akhilles <akhilvelagapudi@gmail.com>
2025-09-15 18:06:28 -04:00

30 lines
510 B
Python

load("@stdlib:v0.2.10/interfaces.zen", "Ground", "Power")
Resistor = Module("@stdlib:v0.2.10/generics/Resistor.zen")
Capacitor = Module("@stdlib:v0.2.10/generics/Capacitor.zen")
SubModule = Module("./sub_module.zen")
vcc = io("VCC", Power)
gnd = io("GND", Ground)
SubModule(
name="sub",
VCC=vcc,
GND=gnd,
)
r1 = Resistor(
name="R",
value="1kOhm",
package="0402",
P1=vcc,
P2=gnd,
)
Capacitor(
name="CAP1",
value="100nF",
package="0402",
P1=vcc,
P2=gnd,
)