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https://github.com/diodeinc/pcb.git
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Akhil Velagapudi
4413c9d4d9
* Hydrate V2 deps during migrate * Fix mixed hydrated package resolution * Simplify workspace discovery * Clean up workspace package discovery naming * Update stdlib formatting paths
77 lines
1.6 KiB
Python
77 lines
1.6 KiB
Python
"""Test for SPICE model of NetTie - demonstrates zero resistance connection."""
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load("../../interfaces.zen", "Ground", "Net", "Power")
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load("../../properties.zen", "Simulation")
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NetTie = Module("../../generics/NetTie.zen")
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Resistor = Module("../../generics/Resistor.zen")
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VCC = Power()
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NET1 = Net()
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NET2 = Net()
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PROBE = Net()
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GND = Ground()
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# Create a 2-pin net tie connecting two nets
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NetTie(
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name="NT1",
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variant="2_SMD_0.5mm",
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P1=NET1,
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P2=NET2,
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)
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# Add resistors to demonstrate the net tie connection
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Resistor(
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name="R1",
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value="1kOhm",
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package="0603",
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P1=VCC,
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P2=NET1,
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)
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Resistor(
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name="R2",
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value="1kOhm",
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package="0603",
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P1=NET2,
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P2=PROBE,
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)
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Resistor(
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name="R3",
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value="1kOhm",
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package="0603",
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P1=PROBE,
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P2=GND,
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)
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Simulation(
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name="test_NetTie",
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setup=f"""
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# Test NetTie SPICE model - should show near-zero voltage drop across net tie
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V1 {VCC} {GND} DC 5V
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.control
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# DC operating point analysis
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op
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# Print voltages to verify net tie behavior
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print v({VCC}) v({NET1}) v({NET2}) v({PROBE})
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# DC sweep to show voltage division
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dc V1 0 5 0.1
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# Save the output to SVG
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set hcopydevtype = svg
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hardcopy output/nettie.svg v({NET1}) v({NET2}) v({PROBE}) title "NetTie Test - Voltage Division" xlabel "Input Voltage" ylabel "Node Voltages"
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.endc
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""",
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)
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# pcb:sch NT1.NT x=456.2000 y=-166.1000 rot=0
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# pcb:sch R1.R x=369.8400 y=-128.0000 rot=0
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# pcb:sch R2.R x=547.6400 y=-128.0000 rot=0
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# pcb:sch R3.R x=712.7400 y=-128.0000 rot=0
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# pcb:sch GND.1 x=710.2000 y=-1.0000 rot=0
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# pcb:sch VCC.1 x=283.4800 y=-216.9000 rot=0
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