mirror of
https://github.com/diodeinc/pcb.git
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Akhil Velagapudi
4413c9d4d9
* Hydrate V2 deps during migrate * Fix mixed hydrated package resolution * Simplify workspace discovery * Clean up workspace package discovery naming * Update stdlib formatting paths
83 lines
2.2 KiB
Python
83 lines
2.2 KiB
Python
"""Test for Spice model of Resistor."""
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load("../../amplifiers.zen", "level_shifter", "sallen_key_lowpass")
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load("../../interfaces.zen", "Ground", "Net", "Opamp", "Power")
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load("../../properties.zen", "Simulation")
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OperationalAmplifier = Module("../../generics/OperationalAmplifier.zen")
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Resistor = Module("../../generics/Resistor.zen")
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VP = Power()
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VN = Power()
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INPUT_SIGNAL = Net("INPUT")
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PROBE = Net()
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GND = Ground()
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VOFFSET = Net()
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OPA1, OPA2 = level_shifter(
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name="OPAMP",
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GND=GND,
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IN=INPUT_SIGNAL,
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OUT=PROBE,
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VOFFSET=VOFFSET,
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gain=1.0,
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)
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# 1V offset for level shifting
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Resistor(name="R1", value="110kOhm", package="0603", P1=VP, P2=VOFFSET)
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Resistor(name="R2", value="10kOhm", package="0603", P1=VOFFSET, P2=GND)
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OperationalAmplifier(
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name="BUFFER",
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VP=VP,
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VN=VN,
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OPA1=OPA1,
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)
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OperationalAmplifier(
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name="SUM",
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VP=VP,
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VN=VN,
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OPA1=OPA2,
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)
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Simulation(
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name="test_LevelShifter",
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setup=f"""
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V1 {VP} {GND} DC 12V
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V2 {VN} {GND} DC -12V
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V3 {INPUT_SIGNAL} {GND} DC 1 SIN(0 1V 1000)
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.control
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* Time domain analysis - show 5 cycles of 1kHz signal
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tran 10u 5m
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* Save output as SVG
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set hcopydevtype = svg
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* Time domain plot of input and output
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hardcopy output/levelshifter.svg v({INPUT_SIGNAL}) v({VOFFSET}) v({PROBE}) title "Level Shifter - Time Domain Response" xlabel Time ylabel Voltage
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.endc
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""",
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)
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# pcb:sch OPAMP_SUM_RF.U x=230.1400 y=227.6000 rot=270
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# pcb:sch OPAMP_SUM_RI.U x=128.5400 y=278.4000 rot=0
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# pcb:sch BUFFER.U x=-204.2000 y=227.6000 rot=0
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# pcb:sch OPAMP_SUM_RA.U x=217.4400 y=176.8000 rot=270
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# pcb:sch OPAMP_SUM_RB.U x=128.5400 y=240.3000 rot=0
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# pcb:sch OPAMP_SUM_RI0.U x=14.2400 y=11.7000 rot=270
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# pcb:sch OPAMP_SUM_RI1.U x=14.2400 y=-64.5000 rot=270
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# pcb:sch R1.R x=-315.9600 y=189.5000 rot=0
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# pcb:sch R2.R x=-315.9600 y=291.1000 rot=0
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# pcb:sch SUM.U x=164.1000 y=-1.0000 rot=0
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# pcb:sch GND.1 x=-318.5000 y=392.7000 rot=0
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# pcb:sch GND.2 x=126.0000 y=329.2000 rot=0
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# pcb:sch VN_VCC.1 x=-161.0200 y=367.3000 rot=180
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# pcb:sch VN_VCC.2 x=207.2800 y=113.3000 rot=180
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# pcb:sch VP_VCC.1 x=-313.4200 y=113.3000 rot=0
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# pcb:sch VP_VCC.2 x=207.2800 y=-13.7000 rot=0
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# pcb:sch VP_VCC.3 x=-161.0200 y=189.5000 rot=0
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