mirror of
https://github.com/diodeinc/pcb.git
synced 2026-09-14 20:17:19 +08:00
Akhil Velagapudi
4413c9d4d9
* Hydrate V2 deps during migrate * Fix mixed hydrated package resolution * Simplify workspace discovery * Clean up workspace package discovery naming * Update stdlib formatting paths
72 lines
1.8 KiB
Python
72 lines
1.8 KiB
Python
"""Test for Spice model of Resistor."""
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load("../../amplifiers.zen", "inverting_sum", "sallen_key_lowpass")
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load("../../interfaces.zen", "Ground", "Net", "Opamp", "Power")
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load("../../properties.zen", "Simulation")
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OperationalAmplifier = Module("../../generics/OperationalAmplifier.zen")
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Resistor = Module("../../generics/Resistor.zen")
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VP = Power()
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VN = Power()
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INPUT_SIGNAL = Net()
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INPUT_OFFSET = Net()
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STAGE = Net()
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INVERTING_SUM = Net()
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GND = Ground()
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VOFFSET = Net()
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OPA1 = inverting_sum(
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name="OPAMP",
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GND=GND,
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INPUTS=[INPUT_SIGNAL, INPUT_OFFSET],
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OUT=INVERTING_SUM,
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gain=1.0,
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)
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OperationalAmplifier(
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name="INVERTING_SUM",
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VP=VP,
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VN=VN,
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OPA1=OPA1,
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)
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Simulation(
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name="test_InvertingSum",
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setup=f"""
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* Establish ground as a 0v node
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V0 {GND} DC 0V
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* Power rails +/- 12V
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V1 {VP} {GND} DC 12V
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V2 {VN} {GND} DC -12V
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* Input source
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V3 {INPUT_SIGNAL} {GND} DC 1 SIN(0 1V 1000)
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V4 {INPUT_OFFSET} {GND} DC 3
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.control
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* Time domain analysis - show 5 cycles of 1kHz signal
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tran 10u 5m
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* Save output as SVG
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set hcopydevtype = svg
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* Time domain plot of input and output
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hardcopy output/inverting_sum.svg v({INPUT_SIGNAL}) v({INPUT_OFFSET}) v({INVERTING_SUM}) title "Inverting Sum - Time Domain Response" xlabel Time ylabel Voltage
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.endc
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""",
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)
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# pcb:sch BUFFER.U x=-204.2000 y=227.6000 rot=0
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# pcb:sch OPAMP_R_F.U x=-49.2600 y=443.5000 rot=270
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# pcb:sch OPAMP_R_I0.U x=-417.5600 y=380.0000 rot=270
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# pcb:sch OPAMP_R_I1.U x=-417.5600 y=291.1000 rot=270
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# pcb:sch INVERTING_SUM.U x=-166.1000 y=189.5000 rot=0
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# pcb:sch OPAMP_R_F.R x=-49.2600 y=430.8000 rot=270
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# pcb:sch OPAMP_R_I0.R x=-430.2600 y=278.4000 rot=270
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# pcb:sch OPAMP_R_I1.R x=-430.2600 y=354.6000 rot=270
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# pcb:sch GND.1 x=-255.0000 y=253.0000 rot=0
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# pcb:sch VN_VCC.1 x=-122.9200 y=341.9000 rot=180
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# pcb:sch VP_VCC.1 x=-122.9200 y=151.4000 rot=0
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