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https://github.com/diodeinc/pcb.git
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Akhil Velagapudi
4413c9d4d9
* Hydrate V2 deps during migrate * Fix mixed hydrated package resolution * Simplify workspace discovery * Clean up workspace package discovery naming * Update stdlib formatting paths
82 lines
2.4 KiB
Python
82 lines
2.4 KiB
Python
"""Test for SPICE model of Capacitor - verifies ESR/ESL parasitic behavior."""
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load("../../interfaces.zen", "Ground", "Net", "Power")
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load("../../properties.zen", "Simulation")
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Capacitor = Module("../../generics/Capacitor.zen")
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Resistor = Module("../../generics/Resistor.zen")
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VIN = Power()
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PROBE = Net()
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GND = Ground()
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# 100nF 0603 MLCC in a simple voltage-divider-like test fixture
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Capacitor(
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name="C1",
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package="0603",
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value="100nF",
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P1=VIN,
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P2=PROBE,
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)
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# Load resistor to set DC bias point
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Resistor(
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name="R_LOAD",
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value="1kOhm",
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package="0603",
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P1=PROBE,
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P2=GND,
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)
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Simulation(
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name="test_Capacitor",
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setup=f"""
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* 1V AC stimulus for impedance sweep
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V1 {VIN} {GND} DC 0 AC 1
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.control
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* --- AC sweep: verify capacitor impedance profile ---
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* A 100nF 0603 cap should show:
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* - Capacitive behavior below ~20MHz (|Z| falling)
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* - Self-resonant dip around 20-25MHz (where ESL cancels C)
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* - Inductive behavior above SRF (|Z| rising)
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ac dec 200 1k 1g
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* Measure impedance at key frequencies via voltage across R_LOAD
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* At low freq, cap is high-Z so most voltage appears across it, PROBE ~ 0V
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meas ac gain_1k find vdb({PROBE}) at=1k
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meas ac gain_10M find vdb({PROBE}) at=10Meg
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meas ac gain_100M find vdb({PROBE}) at=100Meg
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* At 1kHz the 100nF cap has |Xc| ~ 1.6kOhm, so PROBE should be well below 0dB
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* (voltage divider with 1k load)
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if gain_1k > -1
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echo "FAIL: 1kHz gain too high: $&gain_1k dB (capacitor should have significant reactance at 1kHz)"
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quit 1
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end
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* At 10MHz the cap should be low impedance (approaching ESR),
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* so PROBE should be close to 0dB (most signal passes through)
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if gain_10M < -3
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echo "FAIL: 10MHz gain too low: $&gain_10M dB (capacitor should be low impedance near SRF)"
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quit 1
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end
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* Above SRF the ESL takes over -- at 100MHz the cap becomes inductive
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* and gain should drop somewhat compared to at SRF
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* (but this is model-dependent so we just check it's still reasonable)
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echo "PASS: gain(1kHz)=$&gain_1k dB, gain(10MHz)=$&gain_10M dB, gain(100MHz)=$&gain_100M dB"
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set hcopydevtype = svg
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hardcopy output/capacitor.svg vdb({PROBE}) title "Capacitor Impedance Response (100nF 0603)" xlabel Frequency ylabel Magnitude
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* --- Transient test: step response through cap ---
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tran 10n 10u uic
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set hcopydevtype = svg
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hardcopy output/capacitor_transient.svg v({VIN}) v({PROBE}) title "Capacitor Step Response" xlabel Time ylabel Voltage
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.endc
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""",
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)
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