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https://github.com/diodeinc/pcb.git
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Akhil Velagapudi
f20ac95f64
* Add structured, unmatched BOM export command Run using `pcb bom <path/to/zen> -o json` Signed-off-by: akhilles <akhilvelagapudi@gmail.com> * Test bom command in CI Signed-off-by: akhilles <akhilvelagapudi@gmail.com> * Bump stdlib in examples from v0.2.0 to v0.2.2 Signed-off-by: akhilles <akhilvelagapudi@gmail.com> * Remove default_multiplier, use struct for group key Signed-off-by: akhilles <akhilvelagapudi@gmail.com> * Use PhysicalValue to do less string parsing Signed-off-by: akhilles <akhilvelagapudi@gmail.com> * Add alternatives to group key Signed-off-by: akhilles <akhilvelagapudi@gmail.com> * Use DynamicFullWidth for the comfy table Attempts to fit the table within terminal width. Signed-off-by: akhilles <akhilvelagapudi@gmail.com> --------- Signed-off-by: akhilles <akhilvelagapudi@gmail.com>
90 lines
2.9 KiB
Plaintext
90 lines
2.9 KiB
Plaintext
"""
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Type: Gate Driver
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Description: L6387E - High voltage high and low side driver with integrated bootstrap diode for driving N-Channel Power MOSFETs or IGBTs up to 600V
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Features:
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- High voltage rail up to 600V
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- dV/dt immunity ±50V/nsec in full temperature range
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- Driver current capability: 400mA source, 650mA sink
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- Switching times 50/30 nsec rise/fall with 1nF load
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- CMOS/TTL Schmitt trigger inputs with hysteresis and pull down
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- Internal bootstrap diode
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- Outputs in phase with inputs
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- Interlocking function to prevent simultaneous turn-on
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"""
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load("@stdlib:v0.2.2/interfaces.zen", "Power", "Ground", "Gpio")
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Capacitor = Module("@stdlib:v0.2.2/generics/Capacitor.zen")
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# Configuration options
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ImplementationType = enum("NO_PASSIVES", "WITH_PASSIVES")
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Package = enum("DIP", "SOIC")
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implementation_type = config("implementation_type", ImplementationType, default=ImplementationType("WITH_PASSIVES"), optional=True)
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package = config("package", Package, default=Package("SOIC"))
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bootstrap_cap_value = config("bootstrap_cap_value", str, default="100nF 10%")
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# Component configuration mapping
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component_config = {
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"symbols": {
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Package("SOIC"): Symbol(library = "./L6387ED.kicad_sym"),
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},
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"footprints": {
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Package("SOIC"): "Package_SOIC:SOIC-8_3.9x4.9mm_P1.27mm",
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},
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"mpns": {
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Package("DIP"): "L6387E",
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Package("SOIC"): "L6387ED",
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},
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}
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# Properties
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properties = config("properties", dict, optional=True)
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# IO ports
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lin = io("lin", Gpio) # Low side driver logic input
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hin = io("hin", Gpio) # High side driver logic input
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vcc = io("vcc", Power) # Low voltage power supply (max 17V)
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gnd = io("gnd", Ground) # Ground
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LVG = io("LVG", Net) # Low side driver output
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OUT = io("OUT", Net) # High side driver floating reference (max 580V)
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HVG = io("HVG", Net) # High side driver output
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VBOOT = io("VBOOT", Net) # Bootstrap supply voltage (VBOOT-OUT ≤ 17V)
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# Get the appropriate symbol and configuration
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symbol = component_config["symbols"][package]
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footprint = component_config["footprints"][package]
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mpn = component_config["mpns"][package]
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# Create the component
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Component(
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symbol=symbol,
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name=mpn,
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footprint=footprint,
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mpn=mpn,
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pins={
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"LIN": lin.NET,
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"HIN": hin.NET,
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"VCC": vcc.NET,
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"GND": gnd.NET,
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"LVG": LVG,
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"OUT": OUT,
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"HVG": HVG,
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"VBOOT": VBOOT,
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}
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)
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# Add passive components if configured
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if implementation_type == ImplementationType("WITH_PASSIVES"):
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# Bootstrap capacitor
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# Based on datasheet recommendation, CBOOT should be much larger than the external
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# MOSFET gate capacitance. A typical value of 100nF is used.
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# For a MOSFET with 30nC gate charge at 10V, the expected voltage drop would be ~300mV.
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Capacitor(
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name="C_BOOT",
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value=bootstrap_cap_value,
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voltage="50V",
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package="0805",
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P1=VBOOT,
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P2=OUT
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) |