Yishen Chen b4aa47b114 Add pcb sim to setup spice simulation from schematics (#56)

2025-08-26 12:06:04 -04:00

..

common

[DIO-301] Add pcb vendor, pcb build --offline (#72)

2025-08-15 12:07:51 -07:00

resources

Starlark -> Zener (#8)

2025-07-02 17:25:45 -04:00

snapshots

Add pcb sim to setup spice simulation from schematics (#56)

2025-08-26 12:06:04 -04:00

assert.rs

Starlark -> Zener (#8)

2025-07-02 17:25:45 -04:00

component.rs

Fix symbols with multiple pads per pin + component orientation on back-side components (#34)

2025-07-18 14:37:05 -04:00

core_load_resolver.rs

Add Path() with allow_not_exist support (#118)

2025-08-26 08:42:00 -07:00

file.rs

Refactor load logic into pcb-zen-core (#33)

2025-07-18 15:12:53 -04:00

input.rs

add signature annotation to modules in netlist (#57)

2025-08-03 21:27:03 -04:00

interface.rs

Initial implementation of interface subclasses + auto-promotion (#89)

2025-08-20 09:27:39 -07:00

load.rs

Starlark -> Zener (#8)

2025-07-02 17:25:45 -04:00

net.rs

Update net naming strategy (#62)

2025-08-08 15:52:15 -04:00

spice_model.rs

Add pcb sim to setup spice simulation from schematics (#56)

2025-08-26 12:06:04 -04:00

symbol.rs

More robust VSCode schematics viewer (#36)

2025-07-20 15:04:49 -04:00

test.rs

Starlark -> Zener (#8)

2025-07-02 17:25:45 -04:00